Post-quantum acceleration
Planned ML-KEM and ML-DSA hardware, supported by NTT and SHAKE/Keccak building blocks. Algorithm correctness and implementation security require independent evaluation.
BHISMA / PROCESSOR DEVELOPMENT
SHAKTI RISC-V PQC
Developing the processor technology behind a stronger hardware trust boundary.
A proposed India-focused secure-processor programme for enterprise, telecom, critical-infrastructure and strategic equipment. RISC-V is the control-compute foundation; dedicated post-quantum blocks are intended to handle cryptographic operations. This is a development programme, not released silicon.
Under development. No benchmark, certification, commercial availability or institutional endorsement is claimed. RISC-V and the SHAKTI ecosystem describe the technical direction, not a claimed partnership.
A defined engineering direction.
Hardware root of trust
Protected key lifecycle, secure boot, authenticated updates, controlled debug and zeroization are design objectives, not validated assurances.
Integrator-facing software
A proposed firmware, SDK and API path for applications to request authorised cryptographic operations without directly handling private keys.
From FPGA to evidence.
- Define the threat model, interfaces and hardware trust boundaries.
- Develop synthesizable accelerator RTL and verification testbenches.
- Demonstrate ML-KEM-768 key generation, encapsulation and decapsulation on FPGA.
- Evaluate performance, implementation attacks and host integration.
- Assess ASIC feasibility after demonstrator evidence; no silicon schedule is committed.
Technology is not a deployment.
The processor programme is distinct from SHAKTI PQC-Key, the physical-token product concept. Neither automatically upgrades an organisation’s existing security. Integration requires compatible applications, protocols, key management, provisioning, revocation and operational controls.
Discuss research or integration →